Adders and multipliers are two main parts of arithmetic units of computer hardware and play important role in Reversible computations. This paper introduces a novel Reversible 4x4 multiplier circuit that is based on an advanced “Partial Product Generation Circuits” (PPGC) with Peres gates only without duplicating gates. Again, an optimized Peres full adder Reversible gate is used in “Reversible Parallel Adder” (RPA) part with accompaniment with the carry save adder technique. Comparison of the proposed design with previous ones shows that the proposed Reversible multiplier improves the quantum parameters. The proposed design shows lower quantum cost and depth with the help of a novel design in PPGC. The circuit cost of the proposed design is a little higher than the best compared design, but the proposed design shows the lowest total cost which is defined as sum of quantum cost and circuit cost. Moreover, the number of gates, garbage input and output has no change regarding to the best compared design. The proposed multiplier can be generalized as an nxn bit multiplication.

Reversible logic circuits have found emerging attentions in nanotechnology, optical computing, quantum computing and low power design. A programmable logic array (PLA) is a universal circuit which is used to implement combinational logic circuits. The main part of a PLA is its AND array. In this study we propose two types of optimized Reversible programmable logic array (RPLA) circuits. The first type is based on a “2-to-4” AND array, and is proposed for the first time. The second type is based on a “3-to-8” AND array. For each type, we bring some different designs. These circuits are compared with the existing counterparts in terms of number of constant inputs and garbage outputs, delay and the quantum cost and are shown that all parameters in proposed circuits are improved.

Reversible logic is a new technology that is considered as an essential requirement for the design of quantum computers. In the calculation unit of computers, multiplication is one of the most frequently used operations. In this paper, we propose new optimized algorithms to design a parity-preserving Reversible Vedic multiplier. Three approaches for designing optimized Reversible Vedic multiplier circuits are proposed which are better than the existing circuits in terms of quantum cost, number of garbage outputs, number of constant inputs, and other criteria. The proposed Reversible Vedic multipliers can be generalized to produce parity-preserving n*n Reversible multiplier. We have also achieved some relations which can calculate the quantum cost, the number of constant inputs, and the number of required garbage outputs for the proposed Vedic circuit of any dimension. We have shown that our proposed Reversible Vedic multiplier in n*n scale is the best compared to the existing Vedic multipliers.

In this paper, we introduce the notion of multiplier in BL-algebra and study relationships between multipliers and some special mappings, likeness closure operators, homomorphisms and (ʘ, Ú)-derivations in BL-algebras. We introduce the concept of idempotent multipliers in BL-algebra and weak congruence and obtain an interconnection between idempotent multipliers and weak congruences. Also, we introduce the special multiplier ap and study some properties. Finally, we show that if A is a boolean algebra, then the set of all multipliers of A is a BL-algebra under some conditions.

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